1. Field of the Invention
Example embodiments of the present invention relate to nonvolatile semiconductor memory devices, for example, nonvolatile semiconductor memory devices providing a more stable program voltage to a source line.
2. Description of the Conventional Art
A conventional NOR-type nonvolatile semiconductor memory device may include nonvolatile memory cell transistors. Each nonvolatile memory cell transistor may include a control gate connected to a word line, a drain connected to a bit line, a source connected to a source line and a floating gate. Conventional NOR-type nonvolatile memory cell transistors may comprise an array of a plurality of memory cells arranged in a matrix. The sources of a plurality of cell transistors may be connected to a single common source line. The sources of the cell transistors in different word lines may be arranged opposite each other in order to share the source line.
Read, erase and program (write) operations may be performed on conventional NOR-type nonvolatile semiconductor memory devices. The program operation may be performed by accumulating electrons in the floating gate of a memory cell transistor. Upon programming, a voltage may be applied to a corresponding control gate and drain, and logic high (voltage) may be applied to a source line, so that the cell transistor may conduct electricity, and thus, channel hot electron (CHE) injection may be performed on the floating gate. However, because sources the cell transistors are connected to a single common source line, the voltage drop in the source line when programming may vary depending on the number of cell transistors to be programmed. Furthermore, if the voltage applied to the source line of respective cell transistors increases upon programming, a disturbance may occur in cell transistors not selected for programming and connected to the same source line as the cell transistors selected for programming.